Transceiver Circuitry
Pin Diagram of MLX90109
Functional Diagram of MLX90109
Adapted Surface Mount MLX90109EDC Transceivers
Adapted Surface Mount MLX90109EDC Transceivers with Pins
External Circuitry to Tag Transceiver IC
Tag Circuit
This circuit requires 5 V and 10 mA for power supplied.
Antenna Output:
- Pin 1
- ASK Modulated Signal with 125 kHz Carrier
Ground/VSS:
- 0 V/Ground to Pin 2
Speed:
- VDD to Pin 3
- Selects Band Limiting Filter 400 Hz-3.6 kHz
Modulation Input:
- 1 kHz Binary Identification TTL Logic Signal
- Unique for Individual Tags
The modulation input is applied to a parallel diode network to pull up the minimum voltage input to the NMOS transistor to 0.8 V. The higher voltage is also pulled down slightly by a diode to allow a path through the NMOS gate. To minimize this effect, a pull up resistor to 5 V was applied after the parallel diode network. The voltage at the drain of the transistor is an inversion of the TTL signal input. The modulation pin is connected to a voltage divider network at the drain of the transistor. This becomes the modulation envelope for the generated ASK signal.
Mode:
- Float to Pin 5
- Non-Applicable, No Data Received
Clock:
- Float to Pin 6
- Non-Applicable, No Data Received
Data:
- Float to Pin 7
- Non-Applicable, No Data Received
VDD:
- 5 V to Pin 8
- Capacitor C1 is a Noise Filter
External Circuitry to Reader Transceiver IC
Reader Circuit
This circuit requires 5 V and 10 mA for power supplied.
Antenna Input:
- Pin 1
- ASK Modulated Signal with 125 kHz Carrier
Ground/VSS:
- 0 V/Ground to Pin 2
Speed:
- VDD to Pin 3
- Selects Band Limiting Filter 400 Hz-3.6 kHz
Modulation:
- RC High Pass Filter Network to Pin 4
- Limits Low Frequency Noise in Antenna
-
Mode:
- Float to Pin 5
- Selects to Directly Issue Filtered Data Stream
Clock Output:
- Pin 6 to Microcontroller and Pull-Up Resistor
- 1 kHz TTL Clock Signal
- Allows for Easy Microcontroller Coordination with Received Signal
Data Output:
- Pin 7 to Microcontroller and Pull-Up Resistor
- Received Inverted 1 kHz Binary Identification TTL Logic Signal
- Unique for Individual Tags
- 280 µs Delay from Modulation Input on Tag
VDD:
- 5 V to Pin 8
- Capacitor C1 is a Noise Filter
Signal Transmission
Tag: Fast Modulation Input and Antenna Output
The modulation is approaching 100% and the time delay is small. This is before the antennae are coupled with each other. The transition from high to low is much greater than that of low to high.
Tag Antenna Output (Blue) and Reader Antenna Input (Yellow)
When the antennae are coupled the amplitude representing zero becomes higher. The modulation is still very visible and effective. Both Antennae have the same signal with a minimal loss of amplitude.
Reader: Antenna Input and Data Output
The inverted output on the Data line from the antenna input is shown. The time delay between the two signals is much more apparent than that within the modulation input and antenna on the tag.
Tag Fast Modulation Input (Yellow) and Reader Data Output (Blue)
The Data Output is inverted from the Modulation Input. There is a slight amplitude loss and a 280 µs time delay in the output. There are no apparent multipath effects on the signal. The ranges of the antennae are so low that there should not be any. The duty cycle of the output is 54% in contrary to the 50% duty cycle of the input. This will have to be taken into account by the microcontroller of the reader when decoding the binary data and identifying proper tag identifications.
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